1. Field of the Invention
The present invention relates to a flash memory interface circuit useful in a semiconductor integrated circuit in, for example, a multi-chip package.
2. Description of the Related Art
It is known art to enclose two (or more) semiconductor integrated circuits or chips in a single package to form a multi-chip package or MCP. One of the two chips is typically a flash memory. The other chip may be a semiconductor integrated circuit that controls access to the flash memory. The two chips are interconnected by internal lead wires, and the controlling chip is connectable to devices external to the package through external leads. FIG. 1 schematically illustrates the controlling chip 1, flash memory chip 2, internal lead wires 3, external leads 4, and pads 345 to which the lead wires are bonded.
The controlling chip includes an interface circuit, referred to as a flash interface, that receives control signals and data from a central processing unit (CPU) through a CPU interface. The received data may convey command information, address information, and information (referred to as write data) to be written in the flash memory chip. The flash interface converts the command information to signals that read, write, or erase data in the flash memory chip. In a read or write operation, the flash interface also generates further flash memory addresses by successively incrementing a starting address received through the CPU interface.
It is not unusual for the central processing unit to continue writing data in the flash memory chip, without erasing any data, until the flash memory cell array is full. The data are stored at successively higher addresses until the maximum address is reached, at which point the write operation must stop. In a conventional flash interface, which unconditionally executes the commands it receives from the central processing unit, this requires the transfer of a stopping command through the CPU interface. To reduce the load on the interface, it would be helpful if this command could be eliminated.
A flash memory chip is typically organized into individually erasable sectors and blocks. It is necessary to keep track of the sectors and blocks that have been erased, so that the same sector or block will not be erased twice consecutively. Aside from wasting time, consecutive erasing can damage or degrade memory cells and lead to data errors. A conventional flash interface, which faithfully executes all CPU commands, cannot prevent this type of damage; it is necessary to rely on the integrity of the central processing unit and its software. CPU software, however, is not always completely reliable.